1. Field of the Invention
This invention relates to reading control in a semiconductor memory device.
2. Description of the Related Art
DRAM and SRAM are used as semiconductor memory devices. As is well known, DRAMs are cheaper and have a higher capacity than SRAMs, but must be refreshed. On the other hand, SRAMs need not be refreshed and are easier to use, but are more expensive and have a lower capacity than DRAMs.
A virtual SRAM (also termed a VSRAM or a PSRAM) is known as a semiconductor memory device that combines the advantages of a DRAM and an SRAM. A virtual SRAM includes a memory cell array that contains dynamic memory cells similar to those in a DRAM and has a built-in refresh controller, such that the refresh operation is performed internally. As a result, the external device (such as a CPU) connected to the virtual SRAM can access (read or write data to or from) the virtual SRAM without being aware of refresh operations. This feature of a virtual SRAM is known as “refresh transparency”.
The virtual SRAM is described in U.S. Pat. No. 6,545,943 B2 disclosed by the applicants, for example.
In the conventional virtual SRAM, a read operation for a memory cell array is executed in response to a read request accompanied with an address change. Specifically, the conventional virtual SRAM determines that an external read request has been issued only if the read request given externally is accompanied with an address change, and executes a read operation. If the external read request does not accompany an address change, the read request is deemed to not have been issued, and no read operation is executed. For example, if a read request that does not accompany an address change is issued after the issuance of a write request, while a write operation corresponding to the write request is executed, a read operation corresponding to the subsequently-issued read request is not executed. As a result, in the case described above, the conventional virtual SRAM cannot output data in response to the subsequently-issued read request.
Furthermore when data is output, a generation of change in address is required for the execution of the read operation in a virtual SRAM as described above, but a generation of change in address is not required in an SRAM. As a result, it is desired that a virtual SRAM is capable of outputting data if a read request not accompanied with an address change is issued.